Field of the Invention
The present invention relates in general to the automatic detection of a data transmission rate in a serial data communication system, and more particularly to an automatic data transmission rate detection circuit for checking whether an error is present in a data transmission rate at the moment that the data transmission rate is detected and allowing the detected data transmission rate if it is checked that no error is present in the detected data transmission rate, thereby enhancing the performance of a control circuit for a hard disk, a floppy disk or a tape.
Description of the Prior Art
Referring to FIG. 1, there is shown, in block form, a conventional circuit for detecting a transmission rate of serial input data. As shown in this drawing, the conventional data transmission rate detection circuit comprises a controller 60 for generating a plurality of control signals under the control of a system control circuit SCC, a clock transmission rate pulse generator 40 for generating a plurality of clock transmission rate pulse signals in response to an external system clock signal CK, and a switch 50 being switched under the control of the controller 60. As being switched, the switch 50 selectively outputs one of the clock transmission rate pulse signals from the clock transmission rate pulse generator 40.
The conventional data transmission rate detection circuit further comprises a delay circuit 10 for delaying serial data from an input line T1 at a delay rate of the clock transmission rate pulse signal selected by the switch 50, a register 20 for applying data to the delay circuit 10 under the control of the controller 60, a transmitter/receiver circuit 30 for transmitting output data from the delay circuit 11 to the system control circuit SCC at a data transmission rate based on the clock transmission rate pulse signal selected by the switch 50, and a detector 70 for exclusive-ORing a value of the serial data from the input line T1 and a value of a 24th bit of the output data from the delay circuit 10 and outputting the exclusive-ORed result to the controller 60.
The operation of the conventional data transmission rate detection circuit with the above-mentioned construction will hereinafter be described with reference to FIGS. 2 to 4F.
FIG. 2 is a view illustrating a bit format of the input serial data based on an AT prompt protocol. In this drawing, the reference numeral 80 indicates an input bit string in which bits are shifted to the right. A series of idle bits of 1 level indicate that no data is transmitted. The reference numeral 91 indicates a waveform of data received for an idle time period. Characters "A" and "T" indicate prompts for determining a baud rate of a received information character string. Each character is expressed in a hexadecimal number. A start bit of 0 level precedes each character, which is followed by a stop bit of 1 level.
FIG. 3 is a flowchart illustrating the operation of the conventional data transmission rate detection circuit. First, the controller 60 performs an initialization operation at step 100. Namely, when the system clock signal CK is applied to the clock transmission rate pulse generator 40 and the serial data from the input line T1 is applied to the delay circuit 10, the controller 60 is enabled in response to a control signal which is applied thereto from the system control circuit SCC through a line T15. As being enabled, the controller 60 outputs a disable signal to the switch 50 through a line T16 to disable it and activates a pulse width measurement operation to detect the serial data from the input line T1 for a 1 bit idle time period. The controller 60 also outputs a control signal to the register 20 through a line T9 so that the register 20 can apply 1 to all 24 bit positions of the delay circuit 10.
At step 101, the controller 60 scans a bit string of the serial data from the input line T1 to detect a level transition from an idle bit of 1 level to a start bit of 0 level.
Upon detecting the level transition, the controller 60 outputs an enable signal to the switch 50 through the line T16 to enable it. In response to the system clock signal CK, the clock transmission rate pulse generator 40 generates a clock transmission rate pulse signal of 307.2 KHz with a delay rate of 3.26 .mu.s by generating 16 pulses per bit at a highest data transmission rate of 19.2 Kbit and outputs the generated clock transmission rate pulse signal of 307.2 KHz to the switch 50 through a line T3. As being enabled, the switch 50 selects the clock transmission rate pulse signal of 307.2 KHz from the clock transmission rate pulse generator 40 through the line T3 and transfers the selected clock transmission rate pulse signal of 307.2 KHz to the delay circuit 10 through lines T7 and T8.
At step 102, a start bit of the serial data with a pulse width of 52 .mu.s and a transmission rate of 19.2 Kbit is shifted to the delay circuit 10 at the delay rate of 3.26 .mu.s of the clock transmission rate pulse signal of 307.2 KHz selected by the switch 50, as shown in FIG. 4A.
At the moment that the start bit is delayed by 24 bits at the delay rate of 3.26 .mu.s of the clock transmission rate pulse signal of 307.2 KHz at step 103, a rising edge of the start bit appears at a 24th bit position 11 of the delay circuit 10 as shown in FIG. 4B. A falling edge of the start bit is followed by the first 1 level bit in the prompt A. As a result, the input line T1 becomes 1 in level and the 24th bit position 11 of the delay circuit 10 becomes 0 in level. Then, the detector 70 performs its exclusive-OR operation with respect to the two values of 0 and 1 and outputs the exclusive-ORed result to the controller 60. In response to the output signal from the detector 70, the controller 60 checks at step 104 whether the value on the input line T1 is equal to that of the 24th bit position 11 of the delay circuit 10.
The controller 60 is programmed to disregard the output signal from the detector 70 until the start bit is delayed by 24 bits at the delay rate of 3.26 .mu.s of the clock transmission rate pulse signal of 307.2 KHz. Because the output signal from the detector 70 is 1 in level indicating that the value on the input line T1 is not equal to that of the 24th bit position 11 of the delay circuit 10 at step 104, the controller 60 recognizes at step 108 through a line T2 the first 1 level bit in the prompt A following the start bit.
The recognition of the first 1 level bit in the prompt A signifies the determination of a proper data transmission rate. As a result, upon recognizing the first 1 level bit in the prompt A, the controller 60 ends the entire operation in FIG. 3 and outputs a data transmission rate detect signal to the system control circuit SCC through the line T15. On the contrary, if the first 1 level bit in the prompt A is not recognized, the controller 60 abandons the present data transmission rate determining operation and then returns to step 100 to perform the initialization operation again to check the next start bit.
On the other hand, if a start bit of the serial data with a pulse width of 104 .mu.s and a transmission rate of 9.6 Kbit is applied to the input line T1 as shown in FIG. 4C under the condition that the clock transmission rate pulse signal of 307.2 KHz on the line T3 selected by the switch 50 are applied to the delay circuit 10 through the lines T7 and T8, then it is shifted to the delay circuit 10 at the delay rate of 3.26 .mu.s of the clock transmission rate pulse signal of 307.2 KHz.
At the moment that the start bit is delayed by 24 bits at the delay rate of 3.26 .mu.s of the clock transmission rate pulse signal of 307.2 KHz at step 103, a 26 .mu.s pulse portion of the start bit is not applied yet to the delay circuit 10 as shown in FIG. 4D. In this case, a rising edge of the start bit appears at the 24th bit position 11 of the delay circuit 10 and a falling edge thereof is not applied yet to the delay circuit 10. As a result, the input line T1 becomes 0 in level and the 24th bit position 11 of the delay circuit 10 becomes 0 in level, too.
Then, the detector 70 performs its exclusive-OR operation with respect to the two values of 0 and 0 and outputs the exclusive-ORed result to the controller 60. In response to the output signal from the detector 70, the controller 60 checks at step 104 whether the value on the input line T1 is equal to that of the 24th bit position 11 of the delay circuit 10.
Because the output signal from the detector 70 is 0 in level indicating that the value on the input line T1 is equal to that of the 24th bit position 11 of the delay circuit 10 at step 104, the controller 60 determines that a proper data transmission rate is not detected and applies the enable signal to the switch 50 through the line T16 to enable it. In response to the system clock signal CK, the clock transmission rate pulse generator 40 generates a lower 1/2 clock transmission rate pulse signal of 153.6 KHz with a delay rate of 6.52 .mu.s and outputs the generated clock transmission rate pulse signal of 153.6 KHz to the switch 50 through a line T4. As being enabled, the switch 50 selects the clock transmission rate pulse signal of 153.6 KHz from the clock transmission rate pulse generator 40 through the line T4 and transfers the selected clock transmission rate pulse signal of 153.6 KHz to the delay circuit 10 through lines T7 and T8 at step 105. Also, the controller 60 outputs a control signal to the register 20 through a line T10 so that the register 20 can apply 1 to the last 8 bit positions of the delay circuit 10 at step 106. Further at step 106, the controller 60 disregards the output signal from the detector 70.
If the lower 1/2 clock transmission rate pulse signal of 153.6 KHz with the delay rate of 6.52 .mu.s is applied to the delay circuit 10 through the lines T4, T7 and T8, the 26 .mu.s pulse portion of the start bit of the serial data with the pulse width of 104 .mu.s is not applied to the delay circuit 10 and the remaining 78 .mu.s pulse portion is applied up to the 16th bit position of the delay circuit 10, as shown in FIG. 4E. If the start bit is further shifted by 8 bits at step 107, the rising edge of the start bit appears at the 24th bit position 11 of the delay circuit 10 and the falling edge thereof is applied to the delay circuit 10, too, as shown in FIG. 4F. As a result, the input line T1 becomes 1 in level and the 24th bit position 11 of the delay circuit 10 becomes 0 in level.
Then, the detector 70 performs its exclusive-OR operation with respect to the two values of 1 and 0 and outputs the exclusive-ORed result to the controller 60. In response to the output signal from the detector 70, the controller 60 checks at step 104 whether the value on the input line T1 is equal to that of the 24th bit position 11 of the delay circuit 10.
Because the output signal from the detector 70 is 1 in level indicating that the value on the input line T1 is not equal to that of the 24th bit position 11 of the delay circuit 10 at step 104, the controller 60 recognizes at step 108 through the line T2 the first 1 level bit in the prompt A following the start bit. The recognition of the first 1 level bit in the prompt A signifies the determination of a proper data transmission rate. As a result, upon recognizing the first 1 level bit in the prompt A, the controller 60 ends the entire operation in FIG. 3 and outputs a data transmission rate detect signal to the system control circuit SCC through the line T15.
On the contrary, if the first 1 level bit in the prompt A is not recognized, the controller 60 abandons the present data transmission rate determining operation and then returns to step 100 to perform the initialization operation again to check the next start bit.
However, the above-mentioned conventional data transmission rate detection circuit must scan all tracks using all given clock transmission rate pulse signals, to determine a transmission rate of data stored in a storage medium. For this reason, the conventional data transmission rate detection circuit has much time required and imposes burden on an input/output device.